High Thermal Assembly Solution for Large FOEB Chiplets Integrated Package in HPC Application

High performance computing (HPC) and networking products have become more functions and need the larger die size, high density transistor and large memory capacity for computing procedure. To reach high calculation speed for networking product, it will need advanced SoC die like 7nm/5nm to reach networking requirement. Currently, design IC house and Semiconductor industry face the limit of Moore’s Law including the challenge of low wafer yield but high wafer cost for advanced SoC wafer preparion. To get higher wafer yield with low cost saving, design IC house prefer to use chiplet to separate function to muti-chips. In order to connect different functional chips and improve the electrical transmission between chips, the heterogeneous/ homogeneous integration package types as chiplet integrated idea come out and become popular, these package can used TSI ( through silicon via interposer), Fan-out Redistribution Layer (FORDL) or Embedded bridge die (EB) as die connection. 2.5D package with a through silicon via interposer is the most popular and already production in market. Based on published HPC products on the market, the package trend are integrated more HBM or die, larger package size with dissipation capacity. The 2.5D disadvantage are high TSI cost and low yield of TSI wafer and complex MEOL (middle end of line) process flow. IC design houses are looking for alterative package of 2.5D to support large chip module package.In this paper, structure is used FORDL (Fan-out Redistribution Layer) structure with small embedded bridge die as signal horizontal connection between die, and TMV (through mold via) structure for vertical connection, this structure is no need complex MEOL process. By using molding interposer to replace silicon interposer will help to control chip module warpage because smaller CTE mismatch with substrate. But there is a thermal concern for FOEB structure, because molding thermal capability is worse than silicon wafer. In this paper, we demonstrate two solution to enhance FOEB package thermal capability to reach end product request. One solution is build thick TMV to replace fine TSV (through silicon via) structure. By selecting suitable Dry film and optimized Litho process, there is no photoresist residue or TMV crack in cross-section. It has thicker RDL and larger diameter TMV are benefit to power ground preference and transmission of electrical signals. The other solution is using BSM (backside metal) and Metal TIM treatment to enhance FOEB package level thermal capability. Metal TIM has better thermal conductive than X23, but poor TIM coverage on interface and die crack risk during HS clamping process. In our test vehicle result, TIM coverage meet criteria at T0 and after reliability test, there is no EMC or UF crack issue and lid delam issue in SAT.FOEB structure with thick TMV and BSM / Metal TIM is success pass reliability test including MSL4, TCJ 3000 cycle and uHAST 264hrs. This chiplet integration solution allows high I/O density, fine L/S, and good heat dissipation capacity for heterogeneous/ homogeneous integration package.