2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS

Analog-to-digital converters (ADC) are extensively used in wireless sensor networks and healthcare electronic devices to monitor long-term signal conditions. It is essential to prolong battery life in these applications by using an energy-efficient ADC. A successive-approximation register (SAR) architecture, mostly composed of digital circuits, can achieve low power under low supply voltages 1,2. Power consumption can be decreased by using either an energy-efficient capacitive-DAC switching method 1 or a low-power comparator with a majority voting technique 2. In this work, a small coarse ADC resolves the MSB bits. Then, a detect-and-skip algorithm and an aligned switching technique are used to reduce the big fine DAC switching energy. The comparator power is also decreased by utilizing a low-power comparator during coarse conversion and a low-noise comparator during fine conversion. As a result, its FoM performance is as low as 0.85fJ/conversion-step, which is about 3 times better than that of the state-of-the-art work 2.