Electrical Fault Localization of High-Density 3D Interconnect Via Chains Through Innovative Sample Preparation

As semiconductor devices continue to scale toward ever-finer pitches, localizing electrical faults in high-density 3D interconnect via chains demands higher imaging resolution than conventional failure analysis setups allow. This article presents an innovative sample preparation approach that addresses this challenge by fabricating low-profile extension electrodes directly on the chip, routing probe pads to the chip edge to free space for high-numerical-aperture objectives — including oil-immersion lenses — during OBIRCH and LICA analysis. Two electrode fabrication methods are described. The approach was successfully demonstrated by localizing a leakage failure in a fine-pitch nanoTSV chain, with TEM analysis confirming partial via fill as the root cause.