Reliability assessment of AMD MicroBlaze-V TMR architecture using fault injection and proton irradiation

This work analyses the robustness of the recent AMD RISC-V processor: MicroBlaze-V. We study the TMR fault tolerant version of the MicroBlaze-V architecture, implemented in an SRAM-based FPGA. The architecture has been evaluated with fault injection and irradiation campaigns using 15 and 230 MeV proton beams. Experimental results show that AMD TMR MicroBlaze-V architecture offers a fast and flexible design process with good error mitigation of faults in the configuration memory. The results obtained show a good correlation between fault injection and proton irradiation campaigns, which may be used for error-rate estimations and precise error mitigation strategies. Overall, AMD TMR MicroBlaze-V has an error detection rate of around 99.84%. Approximately 1% of failures are not warned beforehand, although experimental data show that these errors are related to the memory, which is triplicated. It is calculated that, under the evaluated conditions, the mean time for a system failure is twice the mean time for a non-fatal error to happen. The cross-section is estimated to be 47 and 65 times better for failures with a previous warning compared to failures without warning in experiments with protons of 15 MeV and 230 MeV respectively.