Reliability analysis of clock networks and critical paths under radiation-induced transients using custom simulation tools

The continuous scaling of CMOS technologies has significantly increased the susceptibility of modern Integrated Circuits (ICs) to radiation-induced Single-Event Transients (SETs), particularly in timing-critical structures such as clock distribution networks and critical paths. This work presents a comprehensive reliability analysis methodology that combines physics-based SET generation with timing-aware, probabilistic propagation analysis to accurately assess the vulnerability of large, post-layout designs. Realistic transient voltage waveforms are generated using the PredicSEE tool, capturing device-level radiation effects under representative heavy-ion strike conditions, and are subsequently propagated through clock networks and critical paths using the UPSET framework, which leverages Static Timing Analysis (STA) to model logical, electrical, and timing masking mechanisms. The methodology is evaluated on seven ISPD2012 benchmark circuits, considering both low-effort and high-effort timing-optimized variants. Experimental results demonstrate that clock networks constitute a major source of vulnerability due to limited masking and large fan-out, while critical path susceptibility is governed by the interplay of load balancing, gate-level logic distribution, interconnect parasitics, and clock period. The analysis reveals that timing optimization does not uniformly improve robustness but redistributes vulnerability among the masking mechanisms, improving electrical and logical masking while increasing the latching probability due to reduced clock periods. The framework is further shown to scale to million-cell post-layout designs. Dedicated coverage and runtime analyses confirm the representativeness and tractability of the approach, providing valuable insights for the design of radiation-resilient circuits for safety-critical applications.