FPGA-oriented Two-phase Bundled-data Circular Self-timed Pipeline and Its Refinement

Two-phase bundled-data circular self-timed pipeline (TBCSTP) is an appealing asynchronous circuit because its relatively fast and on-demand data transfer leads to high power-performance efficiency, and its circular data-path can realize not only iterative or recursive operations but also program execution. We have pioneered a circuit design method which enables us to implement TBCSTP on commercial FPGAs offering circuit-level flexibility. The key challenge in FPGA implementation is to reduce the FPGA resources constituting the critical path on which the main transfer control signals propagate because the greater the resources, the worse the effect from longer signal propagation times during the automated place-and-route process. In this paper, we reveal a refinement of the circuit design method for enhancing the potential throughput. We realize shortcuts for the main transfer control signals. We also clarify every intrinsic timing constraint for the static timing analysis on TBCSTP circuits with the shortcuts, as well as a supplementary manipulation technique for managing the standard EDA tool. We implemented the TBCSTP circuits on AMD Zynq-7000 FPGA. Experimental results show that our method causes hardly any increase in power consumption and circuit area and can achieve a pipeline throughput up to approximately 1.2 times higher than the existing version.