Look‐Up Table Framework for p‐ Channel Double‐Gate MOSFETs : Silicon vs. Germanium Evaluation

Device modeling refers to the representation of electronic devices through mathematical equations, equivalent circuits, or look‐up tables (LUTs), supported by sound physical assumptions and reasoning. To simulate any electronic device in a circuit simulator, an accurate model is essential. The double‐gate (DG) MOSFET is considered a promising candidate for future CMOS technologies. For effective integration into CMOS circuits, models for both n‐channel and p‐channel DG MOSFETs are required. Although extensive studies have been conducted on n‐channel DG MOSFETs, limited attention has been paid to their p‐channel counterparts, particularly in the nanoscale regime. Additionally, accurate device simulation requires a well‐calibrated simulation environment, configured using data from standard reference devices. This work focuses on the nanoscale p‐channel DG MOSFET to enable its use in DG‐CMOS circuits for future integrated systems. A device‐level simulation is performed using the device simulator to extract potential distribution and drain current characteristics, with the ultimate goal of developing a LUT‐based model. The p‐channel structure is simulated on a silicon substrate and then replicated using germanium to compare performance. Guidelines for configuring the simulation environment are also provided. The simulation environment is tuned using drift‐diffusion transport, constant mobility, and optimized source/drain (SD) region and electrode lengths to achieve a high level of accuracy. From the simulation study, it was observed that germanium‐based devices are more susceptible to short‐channel effects (SCEs) at the nanoscale. The simulation environment is configured using minimal‐physics models, simple yet accurate numerical methods, and calibrated reference data. Analytical modeling of the p‐channel DG MOSFET also shows high accuracy when compared with reference results. These findings contribute to the enablement‐balanced modeling for DG–CMOS technology.