Progression in FPGA logic blocks towards efficient hybrid architectures

Ever since the introduction of FPGAs in 1980s, they have witnessed a tremendous growth and are being widely accepted as a compelling alternative medium for the design of digital circuits due to their re-programmability and faster time to market. However, the FPGAs suffer from a major drawback that they have significantly less logic density and lower speed-performance as compared to standard cells. These two important FPGA metrics, i.e., speed and area-efficiency, are primarily influenced by the logic block architecture. Hence, the proper selection of FPGA logic block architecture is vital for addressing the speed-area deficiencies. In this paper, a comprehensive literature survey over three decades of FPGA logic block architectures is presented, keeping in view their impact on device's speed and area efficiency. It is observed that there has been a considerable shift in the choice of FPGA designers from identical logic blocks towards hybrid logic blocks comprising different types of logic resources.