This paper presents a set of thermal isolation technologies to provide a measure to thermally insulate low-power temperature-sensitive tiers from the time-varying power dissipation of high-power tier in heterogeneous 3-D integrated circuits. The proposed technologies use an air gap and mechanically flexible interconnects (MFIs) to replace conventional microbumps and underfill. A two-tier testbed is fabricated to emulate a heterogeneous 3-D stack. The results are then benchmarked with a standard 3-D stacking approach that is simulated using finite-volume modeling. Compared with the conventional approach using microbumps and underfill, a temperature reduction of 35.9% can be achieved in the low-power tier by implementing the air gap and MFIs. Four-point and daisy-chain resistances of the MFIs are measured to verify the electrical connectivity between the tiers during temperature cycling.
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Zhang et al. (2015) studied this question.
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