Low-Latency, Low-Complexity Digital Demodulator for Chirp Spread-Spectrum Packet Synchronization

A low-latency, low-complexity digital demodulator is presented for chirp spread spectrum (CSS)-modulated RF packets targeting low-power IoT wireless systems operating in spectrally congested environments. Conventional CSS receivers rely on fast-fourier transform (FFT)-based synchronization and long preamble sequences, resulting in increased latency and computational complexity. To address these limitations, the proposed receiver employs amplitude-domain synchronization using oversampled sub-chirp windows and maximum likelihood estimation without requiring FFT processing. A digital demodulator co-designed with receiver’s fractional-N phase-locked loop (PLL) architecture enables rapid sub-chirp generation and fast frequency settling, while compensation techniques mitigate symbol boundary offset (SBO) error due to PLL non-idealities during synchronization. The proposed system achieves packet synchronization within 17.5 preamble symbol cycles while maintaining symbol boundary offset estimation error below ±1%. Simulation results demonstrate a syncword misdetection probability below 10−3 at SNRs of 9 dB and 1 dB without and with 8× repetition, respectively. In the presence of interferences, the receiver tolerates worst-case in-band signal-to-noise ratio (SIR) levels down to −16.2 dB while consuming 877 µW and 830 µW average power at the digital demodulator, and fractional-N PLL, respectively. Implemented in 65 nm CMOS, the proposed architecture occupies 0.195 mm2 active area.