Hardware implementation of an artificial neural network using field programmable gate arrays (FPGA's)

In this paper, the authors present a hardware implementation of a fully digital multilayer perceptron artificial neural network using Xilinx Field Programmable Gate Arrays (FPGAs). Each node is implemented with two XC3042 FPGAs and a 1 K/spl times/8 EPROM. Training is done offline on a PC. The authors have tested successfully the performance of the network.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>