Study on Current Sharing of SiC MOSFETs Multi‐Chip Parallel Based on Self‐Inductance and Mutual Inductance Coupling

To improve dynamic current imbalance in multi‐chip parallel SiC MOSFET power modules, this paper investigates the impact of inductive coupling on parallel chips' dynamic current under high‐frequency operation. A self‐inductance‐mutual inductance coupling model was established based on a commercial 8‐parallel module. By applying Kirchhoff's Voltage Law (KVL) equations to analyze the module's power and drive circuits during switching, mutual inductance coupling between adjacent lower‐bridge‐arm branches was quantified, identifying source parasitic inductance coupling differences as the core imbalance cause. Using Ampère's Circuital Law, the “reverse inclined bonding wires + chip orientation adjustment” strategy was proposed, reducing inductive coupling without modifying the original layout. This method achieves the effect of reducing inductive coupling while keeping the original module layout unchanged. Joint Ansys Q3D‐Simplorer simulations showed the lower‐bridge‐arm maximum current difference decreased from 17.475 A to 4.21 A. Trial‐manufactured module tests yielded consistent results: 5.71 A maximum current difference and 9.47% imbalance ratio. This study provides theoretical and engineering references for dynamic current‐sharing design in high‐frequency, high‐power‐density SiC multi‐chip parallel modules.