A Two‐In‐One High‐κ p‐Doping Gate Dielectric for Polarity‐Engineered, Ultralow‐Hysteresis WSe ₂ Transistors

P ‐type field‐effect transistors are a key building block for complementary two‐dimensional logic devices. Pristine WSe 2 commonly shows ambipolar transport, hindering high‐performance p‐channel devices. Surface charge transfer doping (SCTD) has emerged as an effective, non‐destructive strategy to tune the polarity of WSe 2 . However, conventional SCTD usually requires an additional dopant overlayer on the channel and/or contacts, introducing extra interfaces and trap states that promote charge trapping–induced hysteresis, while also increasing device footprint and process complexity. Here, we integrated the SCTD characteristics into the gate dielectric layer, achieving a polarity transition from bipolar to p‐type in WSe 2 without an additional doping layer. This interface‐minimized stack yields an ultralow hysteresis window of ≈5.2 mV·(MV·cm −1 ) −1 and a near‐Boltzmann subthreshold swing (SS) down to ≈79 mV dec −1 . High dielectric constant (ɛ≈ 20) and moderate breakdown field (7 MV·cm −1 ) of BiOCl ensure its good ability of gate control. Experiments and first‐principles calculations further show that the p doping effect originates from the type‐II band alignment between BiOCl and WSe 2 , which was further pushed into type‐III under external electric fields. These results establish p‐doping gate dielectrics as a two‐in‐one strategy for compact high‐performance p ‐type 2D transistors.