What question did this study set out to answer?

This research aims to develop a physical blueprint for a balanced-ternary substrate using advanced circuit design principles.

July 12, 2026Open Access

Zamin — PRATIK Ternary Silicon: physicalizing the poised-zero substrate

View Full Paper

Ask AI

Bookmark

This research aims to develop a physical blueprint for a balanced-ternary substrate using advanced circuit design principles.
Creates a three-rail MTCMOS ternary cell library featuring a high-impedance ground for the poised zero-state.
Implements a dual-memristor crossbar and a spatial hash for multi-script token processing in a three-dimensional architecture.
Utilizes finite-element thermal modelling alongside a microfluidic interposer layout generator.
Introduces a SPICE cell library and testbench for design validation with high-temperature modeling accuracy.
Demonstrates effective collision escape routing through vertical connectivity in silicon vias.
Presents a WYSIWYG simulator for user-friendly design testing without external dependencies.

No takes yet. Share an insight, caveat, or question.

Randomized trial showcases novel hardware design for ternary computing substrates, indicating promising advancements.

Abhishek Choudhary (2026) studied this question.

View Full Paper

Ask AI

Bookmark