Parity-Based Error Correction Code with Crosstalk Avoidance and Link Power Reduction for NoC

The performance of Network-on-Chip (NoC) architectures is severely limited by the high dynamic power consumption and interconnect crosstalk with the scaling of deep sub-micron (DSM) technology. The coupling capacitance between wires dominates the self-capacitance in dense interconnects, and the coupling transitions contribute the most to the link power dissipation. In this paper, we propose a new low-power error correction coding scheme called Parity-based Multi-bit Transient Error Correction (PMTEC), which can simultaneously deal with self-transitions and coupling transitions in NoC links. The proposed method reduces the effective switching activity by employing a balanced encoding strategy, unlike existing coding techniques, which typically degrade the signal integrity or impose significant power overheads for particular data patterns. Experimental analysis demonstrates that PMTEC achieves strong link power reductions on various data profiles, including text, image, and video traffic, without the negative overheads of cutting-edge techniques like Duplicated Two-Dimensional Parities (DTDPs) and Crosstalk-Aware Transient Error Correction (CATEC). Furthermore, the codec’s parametric synthesis reveals a very small footprint, taking up only 2472.018 μm2 of silicon area and using a negligible 0.219 μW of power, which are 87.57% and 99.20% reductions over CATEC, respectively. The suggested work offers a scalable and energy-efficient solution for dependable on-chip communication in power-constrained systems, despite requiring a 15.371 ns latency trade-off to correct 8-bit bursts.