Polarity Control of 2D Material-Based Ambipolar Schottky-Barrier Transistors via Simple Channel Stacking

Schottky-barrier (SB) transistors are essential for energy-efficient logic, providing ultra-shallow junctions and steep subthreshold slopes. While fundamental to reconfigurable field-effect transistors (RFETs), existing designs suffer from multigate complexity and parasitic capacitance when tuning the ambipolarity of SB transistors. This study presents a streamlined 2D material stacking approach for controlling the polarity of SB ambipolar transistors. By stacking an ambipolar WSe 2 channel atop an n-type MoS 2 layer, p-type FET is achieved through electrostatic shielding—eliminating the need for complex additional gates. This reduces device footprint and fabrication costs, enabling high-density integration. The approach is validated through numerical simulations and successful CMOS inverter operation, establishing it as a core enabling technology for future AI-driven logic devices with SB ambipolar transistors.