Advances in gate stack development for p-type 2D channel FETs through sacrificial WSe2 bilayer oxidation

Developing ultrathin, low-disorder gate-stacks for two-dimensional (2D) p-type field-effect transistors (pFETs) remains fundamentally challenging due to poor dielectric nucleation, interface defect formation, and uncontrolled threshold voltage (V t ) shifts. Here, we introduce a sacrificial oxidation–enabled gate-stack strategy that overcomes these limitations by employing a synthetic bilayer (SBL) WSe₂ approach, in which the top WSe 2 layer is selectively oxidized to form an ultrathin WOₓ seed layer for high-κ dielectric integration while preserving an intact monolayer (ML) semiconductor channel. Fabrication of an SBL WSe 2 by sequential transfer of ML WSe 2 enables high-performance back-gate (BG) pFETs with low interface trap density (D it ) of (8–11) × 10¹¹ cm⁻² eV⁻¹, subthreshold swing values as low as 65 mV dec⁻¹, and an on/off current ratio exceeding 10⁷. Devices exhibit a median low-field hole mobility of 38 cm² V⁻¹ s⁻¹ with a maximum of 85 cm² V⁻¹ s⁻¹, and deliver record-high on-state currents of 108 μA μm⁻¹ at a technology-relevant overdrive voltage of 1 V, with peak drive currents reaching 690 μA μm⁻¹. Self-limiting plasma oxidation of the SBL WSe₂ selectively converts the sacrificial top layer into a WOₓ interfacial film, enabling uniform high-κ dielectric nucleation and fabrication of ML WSe₂ dual-gate (DG) FETs while preserving p-type channel behavior after gate-stack formation. In addition, V t variability can be effectively minimized by selecting the appropriate plasma type. These results establish sacrificial layer–assisted gate-stack engineering as a viable pathway for scalable 2D p-channel transistor technologies.