Dielectric encapsulation strategy for monolithically stacked MoS2/WSe2 complementary FETs with enhanced threshold voltage control

We report a monolithically stacked complementary field-effect transistor (CFET) composed of a bottom MoS2 n-FET and a top WSe2 p-FET. An h-BN encapsulation strategy is introduced to effectively passivate the bottom MoS2 transistor against material and device deterioration throughout the three-dimensional integration fabrication process, including multiple lithography, etching, and annealing steps. Moreover, the h-BN/SiO2 stack creates a built-in electric field between h-BN and MoS2, enabling a positive threshold voltage (Vth) shift from −3 to −0.5 V and providing good control over Vth dispersion. As a result, the CFETs exhibit minimally skewed operation, achieving a rail-to-rail characteristic with a high voltage gain of up to 35 V·V−1 at a supply voltage (VDD) of 2 V. Furthermore, key logic gates based on the monolithically three-dimensionally stacked FETs, including NAND and NOR gates, are demonstrated, showing robust and reliable logic functionality.