Low-power 2D circuit with multi-layer BEOL interconnects achieved through threshold voltage tuning

To address the critical bottleneck in the application of transition metal dichalcogenides (TMDCs) for very-large-scale integration (VLSI)—specifically, the severe limitation of multi-layer back-end-of-line (BEOL) interconnects on yield and uniformity—this study proposes and experimentally validates an innovative continuous threshold voltage (V th ) tuning strategy. This approach utilizes tunable interlayer dielectric (ILD) layers to achieve precise V th adjustment within a targeted range. By engineering gate metal stacks (Au/Ag/Al) for coarse V th tuning and employing thickness-controlled, low-temperature deposited Al 2 O 3 and SiO 2 ILD layers for fine compensation (+0.40 V to -0.48 V), a sub-350 °C thermal budget process flow was established. Demonstrates circuit yield under multi-layer BEOL interconnects. Yield data were collected from a test array comprising 1,792 registers, spanning configurations from 1-bit to 32-bit. A notable yield of 95.76% was achieved for the 1-bit register. Furthermore, the fully integrated 16-bit Data Pointer Register functional module was comprehensively validated, successfully demonstrating all intended operations, including address generation and data read/write functions. The fabricated circuits exhibited ultralow static power consumption: inverters at 500 pW μm -1 , basic logic cells averaging below 2 nW, and a full adder consuming merely 24 nW. This work systematically demonstrates a viable pathway for enhancing the yield of multi-layer BEOL interconnects and highlights their promising potential for low-power applications, thereby establishing a robust processing foundation for ultra-large-scale two-dimensional digital integrated circuits.