A Novel Two-Port Behavioral Model for I/O Buffer Overclocking Simulation

This paper presents the first behavioral model solution to the computationally efficient simulation of digital I/O buffers under overclocking operation. Our physics-based two-port approach relies on predicting the timing signals that control the activation of the driver's output stage. The identified nonlinear dynamic model operators of the input port replace the concatenated fixed step-input describing functions of the previous table-based I/O buffer information specification and of other parametric approaches. The implemented gray-box model produces more accurate results than the previous methodologies when assessing the signal integrity performance of high-speed digital links in normal and overclocking conditions under various input excitations. However, it still preserves the computational efficiency recognized for its behavioral model predecessors.