Enhanced Synaptic Plasticity in Ferroelectric-Gated Hf-In-Zn-O/Si-Zn-Sn-O Bilayer Thin-Film Transistors

In this study, we report the fabrication and characterization of bilayer HIZO/SZTO thin-film transistors (TFTs) integrated with a ferroelectric P(VDF–TrFE) top gate for neuromorphic applications. Amorphous HIZO and SZTO films were deposited via RF magnetron sputtering under controlled conditions, followed by photolithography, thermal annealing, and sequential metal electrode deposition. Transmission line method (TLM) analysis confirms linear scaling of total resistance with channel length, indicating ohmic contact formation with reduced contact resistance for thicker HIZO layers. Electrical characterization of the bilayer channel shows enhanced field-effect mobility (∼28 and ∼39 cm 2 V –1 s –1 for 3 nm and 6 nm HIZO, respectively) and tunable threshold voltage, accompanied by a trade-off in subthreshold swing and OFF current. Integration of the ferroelectric P(VDF–TrFE) layer, facilitated by an interfacial ZrO 2 film, results in counterclockwise hysteresis in the transfer characteristics and enables stable artificial synaptic behavior with distinct long-term potentiation (LTP) and depression (LTD). The device exhibits gradual conductance modulation with nonlinearity values of NL(LTP) ≈ 4.04 and NL(LTD) ≈ –2.96, a dynamic range of ∼85, and multiple accessible conductance states suitable for analogue weight updates. The intrinsic switching energy is estimated to be in the pJ range. Neural network simulations based on a multilayer perceptron (MLP) architecture with crossbar implementation demonstrate classification accuracy of approximately 89% in NeuroSim and approximately 96% in hardware-aware PyTorch simulations on the MNIST dataset. These results highlight that the proposed bilayer ferroelectric synaptic transistor provides a balanced combination of linearity, dynamic range, and stability, making it a promising candidate for neuromorphic computing applications.