Profile evolution and mechanisms in pulsed-bias plasma etching of high-aspect-ratio silicon pillars for wafer-scale metasurface manufacturing

As dielectric metasurfaces move toward CMOS-compatible wafer-scale manufacturing, the plasma-etch transfer of high-aspect-ratio (HAR) silicon pillars on oxide-containing stacks has become a key challenge for process integration. Here, we investigate ∼10:1 Si pillar etching on a SiO2 underlayer in a 12-in. CMOS production-line environment under continuous-wave (CW) and pulsed-bias conditions. Under CW operation, aspect-ratio-dependent etching (also termed RIE)-lag-induced asynchronous etch-front arrival causes isolated pillars to reach the Si/SiO2 interface earlier than dense regions. The resulting local interface-exposure dwell time promotes foot loss, charge-assisted ion deflection, and mask-related profile degradation, leading to notching and collapse. Pulsed bias modifies this late-stage evolution nonmonotonically: 50% duty preserves vertical propagation and suppresses CW-type collapse, whereas lower duty cycles reduce continuous interface exposure but can induce taper or height-deficient profile loss. To rationalize these observations, we develop a mechanism-oriented two-dimensional feature-scale simulator that tracks etch-front timing, local interface-exposure dwell time, bottom-critical dimension evolution, and charge-assisted foot degradation. Guided by these results, a stage-dependent pulsed recipe using 50% duty for the main-etch step and 30% duty for the over-etch step yields substantially improved vertical pillar profiles. This work provides a process-level framework for interpreting HAR silicon pillar etching on oxide-containing stacks, with implications for silicon photonics, metasurface manufacturing, and other CMOS-compatible nanophotonic platforms.