The open RISC-V Instruction Set Architecture (ISA) is a versatile architecture with a growing number of implementations, including the aerospace sector, where tolerance to Single-Event Upset (SEU) faults is critical. This paper presents the FPGA-based design and implementation of an SEU-tolerant cache memory for integration into RISC-V cores as part of a memory subsystem protection strategy. The proposed architecture incorporates separate instruction and data caches, organized as four-way set-associative with a write-through policy, complemented by Hamming H(39, 32) encoding for single-bit error detection and correction. Two experimental platforms were developed on a ZYNQ-7000 SoC: one dedicated to functional validation of the Hamming modules through controlled error injection and another for the evaluation of the complete system integrated with an internally developed RV32IMAFE core. The results confirm the correction of single errors and the detection of multiple errors while demonstrating performance improvements between 1.42× and 1.67× compared to the baseline RISC-V core.
Gil et al. (Wed,) studied this question.