Thermal Stresses of TSVs With Silicon Post Conductors and Polymer Insulators

Due to the advantages of ease of fabrication, low cost, and potential high reliability, through-silicon-vias (TSVs) using low-resistivity silicon posts as conductors and circular polymer liners as insulators have been developed for 3-D integration of microelectromechanical systems and microsensors. However, the large coefficients of thermal expansion (CTEs) of polymers lead to significant thermal stresses, which may cause silicon cracks. This paper reports the fabrication, thermal stress simulation, and thermal tests of a silicon TSV using benzocyclobutene (BCB) as the insulator. Silicon TSVs with high-aspect-ratio BCB liners have been fabricated by developing a vacuum-assisted filling method to achieve void-free BCB insulators. Finite-element method (FEM) is employed to simulate the thermal stresses caused by the mismatch in the CTE between silicon and BCB. High-temperature curing experiments show that crack in silicon substrates and silicon posts occurs on TSVs with specific dimensions. By correlating the results of FEM simulations and crack tests, the critical stress that causes silicon cracks is revealed, and design guidelines are proposed to achieve crack-free silicon TSVs.