Parallel Multi‐Operand Addition Using CPA‐Trees and Carry‐Select Adders

Multi‐operand addition is a fundamental operation in high‐performance digital systems, with applications ranging from signal processing to cryptography. The classical approach for binary multi‐operand addition employs compression trees followed by a final prefix adder, which achieves high speed but requires irregular structures and complex descriptions. Alternatively, carry‐propagate adder (CPA)–based adder trees offer a more regular structure and facilitate efficient hardware implementation. In this work, we propose an alternative parallel architecture based on CPA‐trees combined with a final carry‐select adder (CSLA), which reduces delay while preserving regularity and synthesis friendliness. ASIC results show that the proposed architecture achieves competitive delay with only a slight area overhead. Furthermore, delay reductions are obtained while maintaining dynamic power and energy‐per‐operation values comparable to those of the conventional CPA‐tree, resulting in an attractive trade‐off between performance, hardware cost, and implementation simplicity. These results make the proposed binary adder trees attractive for ASIC implementations in arithmetic‐intensive applications.