Randomized trial demonstrates improved efficiency in model fine-tuning on Apple Silicon, implying practical AI deployment on consumer-grade hardware.
We present a methodology for parallel LoRA fine-tuning of multiple large language models on a single Apple M2 Ultra workstation with 192GB unified memory. Using the Saif cybersecurity suite—eight 7-billion parameter specialist models (Router, Reverse Engineering, Vulnerability Discovery, Exploit Chain Development, Kernel Security, Browser Security, Web Application Security, and Network Security)—we demonstrate that simultaneous training of up to six LoRA adapters is not only feasible but significantly more efficient than sequential training. Our experiments show that 6 concurrent training runs achieve a total throughput of 3.00 it/s, compared to 1.47 it/s for a single run, representing a 2.04× aggregate throughput improvement. Peak memory consumption across six simultaneous runs reaches approximately 110 GB (57% of available unified memory), leaving headroom for system processes and data pipelines. The complete training pipeline—all eight models, each trained on 50K domain-specific examples for 3,000 iterations—completes in approximately 90 minutes, versus an estimated 5 hours for sequential training. Each trained LoRA adapter occupies 11–23 MB, and fused models are 14.2 GB each in fp16. This work establishes that Apple Silicon's unified memory architecture enables unprecedented parallelism in model fine-tuning, making multi-specialist AI systems practical on consumer-grade hardware.
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Yahya Saqban (2026) studied this question.