Deploying large-scale artificial intelligence models for language processing on edge devices is limited by constraints in computational capacity and energy efficiency. To address this challenge, we present a hardware-algorithm co-design framework that leverages analog in-memory computing and hyperdimensional computing for efficient language identification at the edge. By exploiting the inherent randomness and multistate properties of analog memristors, we implement a vector matrix multiplication-based language feature encoding with much reduced hardware complexity. Language classification is then realized with a single-layer perceptron on analog memristive crossbar arrays, eliminating inter-layer activation functions and backward propagation during training that are required in deep neural networks. Experimental implementation on a multicore memristive system-on-a-chip demonstrates a 90% reduction in hardware resources while achieving 95.24% language identification accuracy, the highest reported among hyperdimensional computing implementations on emerging hardware platforms. This work provides a scalable, energy-efficient approach for high-accuracy language processing on edge devices. Energy-efficient, high-accuracy language processing on edge devices is currently constrained by limited computational capacity. Huang et al. propose a hardware–algorithm co-design that implements a vector–matrix multiplication-based language feature encoding with significantly reduced hardware complexity.
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Huang et al. (2026) studied this question.
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