CRT Dual-Rail Computation: Extended Architecture for Zero-Overhead SIMD and Multi-Prime RNS

This document is a major revision (Version 2.0) of the original CRT dual-rail framework (DOI: 10.5281/zenodo.21617438). While the original work established that a standard binary ALU can simultaneously perform binary and ternary arithmetic via the Chinese Remainder Theorem—yielding a 1.67× throughput gain—it introduced practical overheads including a 12% clock-frequency penalty, a 3-cycle extraction tax, and memory-alignment issues. This extended version presents three architectural enhancements that systematically eliminate these overheads: 1. Carry-Save Accumulator (CSA) Tree: Replaces the standard adder inside the MAC array, deferring carry resolution to the end of the dot product. This removes the carry chain from the critical path, restoring native clock speeds and eliminating the 12% frequency penalty. 2. Self-Tuning Auto-Sensor Governor: A hardware-based replacement for OS-dependent bottleneck controllers. By monitoring the MAC counter, overflow proximity, and thermal gradient, this unit dynamically selects optimal batch ratios (100:1, 300:1, or 1000:1) without software profiling, reducing extraction overhead to below 1.2%. 3. Multi-Prime RNS Calibration: Generalizes the CRT scheme to four primes {2,3,5,7}, deriving the balanced exponent set (16,10,6,5) via brute-force Pareto search. This delivers up to 3.8× SIMD throughput for batch-heavy workloads such as AI inference and DSP. The cumulative effect of these extensions reduces total system overhead to under 1.5%, transforming CRT from a theoretical compromise into a purely multiplicative performance gain suitable for immediate deployment in AI accelerators and data-center hardware. Changes in this version (v2.0): Addition of the Carry-Save Accumulator (CSA) tree to eliminate the clock-frequency penalty. Introduction of the Self-Tuning Auto-Sensor hardware governor for dynamic batching. Generalization to multi-prime RNS with calibrated balanced exponent set (16,10,6,5). Updated bottleneck analysis with quantified mitigations. Revised architectural floorplan reflecting the cost-killing redesigns.