Microbeam mapping of single event latchups and single event upsets in CMOS SRAMs

The first simultaneous microbeam mapping of single event upset (SEU) and latchup (SEL) in the CMOS RAM HM65162 is presented. We found that the shapes of the sensitive areas depend on V/sub DD/, on the ions being used and on the site on the chip being hit by the ion. In particular, we found SEL sensitive sites close to the main power supply lines between the memory-bit-arrays by detecting the accompanying current surge. All these SELs were also accompanied by bit-flips elsewhere in the memory (which we call 'indirect' SEUs in contrast to the well known SEUs induced in the hit memory cell only). When identical SEL sensitive sites were hit farther away from the supply lines only indirect SEL sensitive sites could be detected. We interpret these events as 'latent' latchups in contrast to the 'classical' ones detected by their induced current surge. These latent SELs were probably decoupled from the main supply lines by the high resistivity of the local supply lines.