Efficient VLSI digital logarithmic codecs

N bit digital words can be logarithmically encoded and compressed to a word length of (log2n + m − 1) bit maintaining a relative accuracy of m bit over (n − m) octaves of signal level. A bit-serial VLSI coder is reported, which requires little more than a log2n counter and an output register and it has a latency of one wordlength. The bit-parallel coder can be built with less than n2 transistors and has less than n/4 gate delays. The decoder has similar properties and it expands the logarithm to an antilogarithm with n bit of dynamic range. Using these codecs, digital multiplication, division, powers and roots are reduced to additions, subtractions and shifts, respectively.