Charge-mode parallel architecture for vector-matrix multiplication

An internally analog, externally digital architecture for parallel vector-matrix multiplication is presented. A three-transistor unit cell combines a single-bit dynamic random-access memory and a charge injection device binary multiplier and analog accumulator. Digital multiplication of variable resolution is obtained with bit-serial inputs and bit-parallel storage of matrix elements, by combining quantized outputs from multiple rows of cells over time. A prototype 512/spl times/128 vector-matrix multiplier on a single 3 mm /spl times/3 mm chip fabricated in standard 0.5-/spl mu/m CMOS technology achieves 8-bit effective resolution and dissipates 0.5 pJ per multiply-accumulate.