Spin dependent tunnel junctions for memory and read-head applications

Spin dependent tunnel junctions with TMR exceeding 30-40% can now be prepared with AlO/sub x/ and AlN barriers, with junction resistance tuned from 30-40 /spl Omega//spl times//spl mu/m/sup 2/ to 10/sup 8/ /spl Omega//spl times//spl mu/m/sup 2/. Thermal stability is better than 3000% for thicker barriers (>11 /spl Aring/) but is degraded to 220/spl deg/C for 6 /spl Aring/ barriers. A 9 bit MRAM cell is demonstrated using tunnel junctions and vertically integrated a:Si diodes. Junction switching is achieved with on chip 20 ns field pulses. Requirements for tunnel junctions for 100 Gb/in/sup 2/ read head applications are discussed. First prototypes of tunnel junction read heads with 600 /spl Aring/ read gaps were fabricated, where the TJ is at the air bearing surface. TMR loss was observed during the final head lapping steps.