Technology of RTL product description model development in the development of CAD soft-ware and analytical complex

This is the authors' abstract. We don't add key points for this paper.

The article is devoted to the development of a proprietary CAD system designed for the design of various digital microelectronics devices. The presented works were carried out by VSFEU in cooperation with ROSELECTRONICS Holding. Cadence software was used to simulate a digital microprocessor based on SYNTACORE's 32-bit SCR1 core with the implementation of the IMC instruction set. The synthesis of the RTL model for testing was carried out in automatic mode and included a stage of testing for synthesizability and a stage of direct synthesis. The synthesis was carried out on the basis of standard library elements of the selected technology for the 130 nm process of the HHGRACE factory. For the created model, a test of the connection list (netlist) was performed, while the logical model was replaced by a list of circuits. Then the calculation of the power consumed by the circuit was carried out. At the end of the development, various tests aimed at verifying the correctness of the RTL code were carried out for the ready-made model - tests for compliance with specificity, tests for edge cases (corner case testing), tests based on applied tasks and algorithmic testing (real code testing), as well as tests for pico-high performance and throughput of switches and interfaces.