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A microtunnel diode load for a normally off enhancement mode gallium arsenide field effect transistor provides a compact inverter circuit of fast switching speed and low power consumption. Level shifting is not required, and direct coupling with multiple fan-out causes a comparatively small decrease in speed. The tunnel diode FET logic (TDFL) should be capable of operation at 2 GHz with a power-delay time product of 3.4 fJ for an output node capacitance of 50 fF. The negative characteristic of the tunnel diode combined with the FET provides a compact memory cell. However, advances in the state of the art for producing microtunnel diodes of precisely controlled peak current will be required before a viable TDFL can emerge.
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K. Lehovec (1979) studied this question.
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