Comprehensive Writing Margin Analysis and its Application to Stacked one Diode‐One Memory Device for High‐Density Crossbar Resistance Switching Random Access Memory

The sneak current through the neighboring cells interrupts reading of a selected cell in high‐resistance state in crossbar resistance switching random access memory (RRAM). As the sneak current mainly originates from a parallel resistance component to a selected cell, write operation, which requires sufficiently high voltage delivered to the selected cell, has been regarded to have little relevance to the sneak current issue. In this work, it is revealed that an additional voltage drop on the wire resistances of selected word and bit lines causes an increase in voltage for the write operation (programming/erasing), whose degree is associated with the selectivity of the RRAM selector, array size, resistance of the selected cell, and wire resistances. The presence of sneak paths gives rise to an additional concern about the disturbance of the unselected cells, especially when the writing voltage of the selected cell was increased by the aforementioned factors. A floating voltage scheme is considered for proposing a unified writing margin analysis model with diode selectors, and a feasible design strategy based on the analysis for an experimental RRAM device employing a diode with an extremely high rectification ratio (8.4 × 10 8 ) is provided. Furthermore, application of the model to the universal RRAM devices, irrespective of their switching polarity, selector types, and adopted voltage schemes, is included.