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January 1, 2008IEEE Journal of Solid-State Circuits

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

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Authors

SBSeung-Jun BaeSamsung (South Korea)KPKwang‐Il ParkGyeongsang National UniversityJIJeong-Don IhmSamsung (South Korea)

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Bae et al. (2008) studied this question.

synapsesocial.com/papers/6a71cef231a3df824329d273https://doi.org/10.1109/jssc.2007.908002
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Also Consider

Synapse has enriched 3 closely related papers on similar clinical questions. Consider them for comparative context:

  1. 1Bus-invert coding for low-power I/O1995 · 974 citations
  2. 2A 512-Mb DDR3 SDRAM Prototype With $C_IO$ Minimization and Self-Calibration Techniques2006 · 41 citations
  3. 3A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM1994 · 178 citations