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Three InP MISFETs have been monolithically integrated on an Fe-doped semi-insulating InP substrate in conjunction with three integrated load resistors forming an inverter. The epitaxial layers have been grown by chloride vapour-phase epitaxy. The MISFETs exhibit transconductances as high as 200 mS/mm for a gate length of 1 μm. The circuit consists of one MISFET that is operated as a one transistor-inverter stage in isolation and a two-stage inverter whose output is connected to the gate of an FET. For two-stage inverters we have obtained typical high- and low-level noise margins of 0.4 and 0.3 V at a bias level of 1.5 V.
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Antreasyan et al. (1986) studied this question.
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