3D GaN nanoarchitecture for field-effect transistors

The three-dimensionality of 3D GaN field-effect transistors (FETs) provides them with unique advantages compared to their planar counterparts, introducing a promising path towards future FETs beyond Moore's law. Similar to today's Si processor technology, 3D GaN FETs offer multi-gate structures that provide excellent electrostatic control over the channel and enable very low subthreshold swing values close to the theoretical limit. Various concepts have been demonstrated, including both lateral and vertical devices with GaN nanowire (NW) or nanofin (NF) geometries. Outstanding transport properties were achieved with laterally contacted NWs that were grown in a bottom-up approach and transferred onto an insulating substrate. For higher power application, vertical FETs based on regular arrays of GaN nanostructures are particularly promising due to their parallel integration capability and large sidewall surfaces, which can be utilized as channel area. In this paper, we review the current status of 3D GaN FETs and discuss their concepts, fabrication techniques, and performances. In addition to the potential benefits, reliability issues and difficulties that may arise in complex 3D processing are discussed, which need to be tackled to pave the way for future switching applications. • We review the current status of 3D GaN FETs and discuss their concepts, fabrication techniques, and performances. • Various 3D GaN FETs have been demonstrated, including lateral and vertical GaN nanowire (NW) or nanofin (NF) geometries. • Bottom-up and top-down fabrication and processing methods for 3D GaN FETs have been described. • Vertical GaN FETs nanostructures are promising due to their parallel integration capability and large sidewall surfaces. • Reliability issues and difficulties that may arise in complex 3D processing are discussed.