This study provides a framework to accurately test basic signal processing across various interpolation schemes and compare their power consumption and filtering quality in FPGA devices.
FPGA interpolation filter measurements leave open optimal power-performance schemes; hypothesis-generating for resource-limited DSP designs.
The development of FPGA-based digital signal processing devices has been gaining attention. Researchers seek to reduce power consumption and enhance signal processing quality in these devices with given resources and spatial limits. Hence, there is a need to investigate both the capability and the power consumption associated with the various digital filtering schemes commonly used in FPGA-based devices. We carry out a set of performance and power consumption measurements of interpolation filters using an FPGA and other basic signal processing building blocks. We compare the signal processing performance with theoretical prediction, and measure the power consumed by the filters. Our experimental measurements also confirm the accuracy of the numerical tools used for predicting FPGA power consumption. This paper is aimed at providing a framework to accurately test basic signal processing across various interpolation schemes and compare the respective schemes’ software-side contributions to power consumption and filtering quality.
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Donnelly et al. (2017) studied this question.
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