An Output-Capacitorless Analog LDO Featuring Frequency Compensation of Four-Stage Amplifier

In this paper, we propose an output-capacitorless analog low-dropout voltage regulator (ALDO) featuring frequency compensation of a four-stage amplifier consisting of a three-stage error amplifier (EA) without cascoding plus a last stage formed by a pass transistor (MP). It achieves good output voltage regulation under low supply-voltage (Vdd) with an unsaturatedMP(e.g., dropout voltage of 30 mV under 0.5 V supply) because of the three gain stages in the EA. Frequency compensation is achieved by performing a two-port feedback analysis with the root-locus diagram (TFR) method that provides an intuitive understanding of pole/zero dynamics in thes-plane. Fabricated in 0.18μ mCMOS, the proposed ALDO achieves asymptotic stability over a wide range of operating conditions:Vddof0.5~ 1.8V, load capacitance of 0~50 pF, load current (IL) of 0~2 mA (0~200 mA) underVddof 0.5 V (1.8 V), and temperature of- 20~ 125\,\,∘C. Also, it does not require minimum on-chip output capacitance, thus achieving a small area of 0.0035 mm2. As a result, a good low-frequency PSR of −62 dB with a dropout voltage of 30 mV and a state-of-the-art current density of 11.4 A/mm2 are achieved.