Design and Test of a Low Junction-to-Case Thermal Resistance Packaging Method

This is the authors' abstract. We don't add key points for this paper.

Further development of integrated circuits (ICs) is greatly limited by the thermal problems inherent to chips. To eliminate the large thermal resistance between the contact surfaces of the components, thermal interfacial material (TIM) is widely used to enhance the thermal performance of packages. However, the existing TIM materials have performance problems such as low thermal conductivity, internal structural defects, and aging behavior and delamination after long-term use. These shortcomings have become important factors that hinder the improvement of heat dissipation of chips. This article proposes a low junction-to-case thermal resistance packaging method of introducing a fluid phase change in the package, which utilizes latent heat to efficiently transfer heat while eliminating the TIM layer and the thermal resistance introduced by it. Theoretically, the novel method has the potential to obtain a low thermal resistance of 0.031 °C/W and greatly reduces the thermal resistance of the inner structures of the package except for the die and lid. A Si-Al package sample with a total thickness of 2.9 mm was fabricated, and the influence of phase-change heat transfer on the thermal resistance of the junction case was tested with a silicon-based thermal test chip (TTC) as the heat source. In the experiment, this method reduces the thermal resistance of the sample from ~0.46 to ~0.1 °C/W under a 3-W power input.