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In-memory computing (IMC) has been identified as a promising paradigm for hardware neural network accelerators thanks to the reduced data movement and improved parallelism. A known issue of IMC is the relatively large summation current within the memory array, which causes energy inefficiency and computing inaccuracy due to IR drop. An additional burden is the area and energy-demanding readout circuits, which limit the density and energy efficiency of computing. This work reports a hardware demonstration of IMC using 3-D crosspoint (3DXP) arrays of ovonic threshold switches and phase change memories (PCMs). We demonstrate a precise program–verify (PV) algorithm optimized for the subthreshold regime, allowing for a reduction of the operating currents by more than two orders of magnitude with respect to the conventional 3DXP technology. We experimentally demonstrate vector–vector multiplication (VVM) and feature extractions, which are key operations of convolutional neural networks (CNNs). Simulation study of LeNet5 with binary and ternary quantization, including device variability, 1/f noise, and drift, demonstrates high accuracy and low-energy inference thanks to precise programming, subthreshold operation, and careful drift compensation.
Carletti et al. (Wed,) studied this question.