Single‐Step Analog In‐Memory Matrix Computation in Three‐Dimensional Circuits

Analog in‐memory computing offers an energy‐efficient solution to resource‐intensive matrix operations in artificial neural networks by performing multiplication via Ohm's law and summation via Kirchhoff's current law. However, two‐dimensional (2D) computing fabrics require unrolling of 2D input into one‐dimensional vectors, demanding an auxiliary memory and diminishing the overall efficiency. Herein, we propose three‐dimensional (3D) architectures that enable single‐step matrix operations without data unrolling. Our proposed hardware interfaces with 2D inputs and outputs directly, allowing data flow seamlessly across the stacked layers. We experimentally validate this concept for matrix‐kernel convolution (MKC) for image processing using both a transistor‐based system on a printed circuit board and a 3D memristive array, and we describe and analyze matrix to matrix multiplication (MMM) as a supported architectural mapping. Our 3D designs are stackable and scalable, enabling parallel multilayer matrix operations in a single step and thereby yielding reduced hardware complexity while delivering over 113‐fold energy savings and orders‐of‐magnitude improvement in operational latency.