A 2.6-GByte/s multipurpose chip-to-chip interface

A 2.6 GByte/s megacell that interfaces to single or double byte wide DRAMs or logic chips is implemented using 0.35-0.18 /spl mu/m CMOS technologies. Special I/O circuits are used to guarantee 800 Mbit/s/pin data rate. Microwave PC board design methodologies are used to achieve the maximum possible interconnect bandwidth.