A 10-nW 12-bit accurate analog storage cell with 10-aA leakage

Medium-term analog storage offers a compact, accurate, and low-power method of implementing temporary local memory that can be useful in adaptive circuit applications. The performance of these cells is characterized by the sampling accuracy and voltage droop that can be achieved with a given level of die area and power. Hand calculations suggest past implementations have not achieved minimum voltage droop due to uncompensated MOS leakage mechanisms. In this paper, the dominant sources of MOS leakage are experimentally characterized in a standard 1.5-/spl mu/m CMOS process using an on-chip current integration technique, focusing specifically on the 1 fA to 1 aA current range. These measurements reveal an accumulation-mode source-drain coupling mechanism that can easily dominate diode leakage under certain bias conditions and may have limited previous designs. A simple rule-of-thumb is offered for avoiding this leakage effect, leading to a novel ultra-low leakage switch topology. A differential storage cell incorporating this new switch achieves an average leakage of 10 aA at room temperature, an 8/spl times/ reduction over past designs. The cell loses one bit of voltage accuracy, 700 /spl mu/V on a 12-bit scale and 11.3 mV on an 8-bit scale, in 3.3 and 54 min, respectively. This represents a 15/spl times/ increase in hold time at these voltage accuracies over the lowest leakage cell to date, in only 92% of the area. Since the leakage is independent of amplifier bias, the cell can operate on as little as 10 nW of power. Initial measurements also indicate the switch's leakage decreases with the square of process feature size.