Practical lot release methodology for semiconductor back-end manufacturing

This paper presents a new method and system that has been developed to solve production lot release problems in a discrete semiconductor back-end manufacturing environment, wherein there is always a huge product mix and a multitude of capacity constraints. The methodology is a multi-constraint based finite capacity production control mechanism to plan lot release of the desired mix of products for the semiconductor assembly and test operations. Practical lot prioritization considerations, order release policies, finite capacity constraints and a novel technique of multi-level loading pattern for minimizing machine conversion are discussed in detail. The system and methodology presented in this paper has been successfully implemented in a semiconductor back-end factory in Asia.