Systematic design for optimization of high-speed self-calibrated pipelined A/D converters

High-speed pipelined analog-digital converters have been previously considered using optimum 1-bit per stage architectures that typically can attain untrimmed resolution of up to 10 bits. Conversion resolutions higher than 10 bits can only be achieved if calibration techniques are employed. In this case, however, this paper demonstrates that multibit, rather than single-bit resolution per-stage architectures have to be considered for optimizing the resulting area and power dissipation while minimizing stringent requirements of the constituting building blocks. Such optimization is achieved through a systematic design process that takes into account physical limitations for practical integrated circuit implementation, including thermal noise and capacitor matching accuracy. The impact of the selected pipelined configuration on the self-calibration requirements as well as on the practical feasibility of the active components is analyzed. An example is presented to consolidate the relevant conclusions.