Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 μm CMOS technology

An electrostatic discharge (ESD) evaluation of a silicided 0.25 μm complementary metal-oxide-semiconductor (CMOS) technology is carried out by HBM, CDM, and TLP tests. Good ESD hardness and device performance are obtained by using retrograde-like well profiles. It is shown that devices with minimum gate length do not necessarily give the best ESD-results. This is due to a difference in failure mechanism between the shortest and the longer channel devices and possibly by a more homogeneous snapback of the slightly longer devices.