Reconfigurable In-Memory Computing Using Standard 6T SRAM for BCAM, TCAM, Similarity Indexing, and Logic-in-Memory Operations

In-memory computing (IMC) has emerged as a promising paradigm to overcome the von Neumann bottleneck by performing computations directly within memory, thereby significantly reducing data movement and enhancing energy efficiency. Among various memory technologies, SRAM-Content Addressable Memories (CAMs) based IMC stands out due to its high-speed operation and compatibility with existing CMOS technology. Nevertheless, existing SRAM-CAM based IMC architectures often encounter trade-offs between computational accuracy, stability, and energy efficiency, which hinders their widespread adoption. To tackle these limitations, the proposed reconfigurable SRAM (R-SRAM) architecture integrates both analog and digital computation, utilizing a standard SRAM array alongside a modified peripheral circuit to support multiple functionalities. These include conventional SRAM operation, Binary and Ternary CAM (BCAM and TCAM), similarity index computation, and bitwise logical operations such as AND, NOR, and inversion (INV). Comprehensive post-layout simulations with Monte Carlo statistical analysis for 22nm FDSOI foundry process technology are performed to validate functionality, robustness, and performance. Simulation results indicate a significant improvement in energy per operation, measured at 0.44 femtojoules (fJ)/bit for the BCAM/TCAM search operation, while adding minimal area overhead and maintaining cell stability during computation. These findings underscore the potential of hybrid SRAM-based IMC architectures for next-generation low-power computing, especially for AI applications.