Radiation-hardened 8T SRAM-based In-memory computing architecture

This work presents an 8T SRAM-based 4 × 4 array for boolean logic, binary content addressable memory/ternary content addressable memory (BCAM/TCAM) searching, and In-memory computation (IMC). The proposed cell-based memory array can execute bit-wise logical operations like “AND”, “NAND”, “OR”, “NOR”, “XOR”, and “XNOR”. It also includes the functionality for performing binary addition and conversion between binary and gray code. Read noise margin and half select concerns are much improved by the decoupled differential read approach. The proposed cell has the highest critical charge Q crit due to current carrying capability enhancement due to the addition of two transistors. The proposed radiation hardened In-memory computing 8T SRAM (RHMC8T) has 1.04 × , 0.96 × , 0.72 × , and 2.78 × better read stability, access time, write access time and Q crit , than the Split-6T SRAM cell.